/*-----------------------------------------------------------------------
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							   \\  - -  //
								(  @ @  )
+-----------------------------oOOo-(_)-oOOo-----------------------------+
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2013-20xx CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		http://blog.chinaaet.com/crazybingo
Email Address 		: 		thereturnofbingo@gmail.com
Filename			:		MCU2FPGA_SPI_Test.v
Data				:		2013-07-18
Description			:		Test SPI Communication between FPGA and MCU.
Modification History	:
Data			By			Version			Change Description
=========================================================================
13/07/18		CrazyBingo	1.0				Original
13/10/17		CrazyBingo	1.1				Modification
-------------------------------------------------------------------------
|                                     Oooo								|
+------------------------------oooO--(   )-----------------------------+
                              (   )   ) /
                               \ (   (_/
                                \_)
----------------------------------------------------------------------*/   

`timescale 1ns/1ns
module MCU2FPGA_SPI_Test
(
	//global clock 50MHz
	input			clk,			//50MHz
	input			rst_n,			//global reset
	

	//user interface
	//mcu spi interface, mcu is master
	input			spi_cs,			//Chip select enable, default:L
	input			spi_sck	,		//Data transfer clock
	output			spi_miso,		//Master input and slave output
	input			spi_mosi,		//Master output and slave input	
	
	//74595 led interface
	output			led595_dout,	//74hc595 serial data input	
	output			led595_clk,		//74hc595 shift clock (rising edge)
	output			led595_latch	//74hc595 latch clock (rising edge)
);


//----------------------------------
//sync global clock and reset signal
wire	clk_ref;
wire	sys_rst_n;
system_ctrl_pll	u_system_ctrl_pll
(
	.clk			(clk),			//50MHz
	.rst_n			(rst_n),		//global reset
	.clk_c0			(clk_ref),			//100MHz	
	.sys_rst_n		(sys_rst_n)		//system reset
);


//-----------------------------------
//Receive SPI Data from mcu.
wire			rxd_flag;
wire	[7:0]	rxd_data;
spi_receiver	u_spi_receiver
(
	//global clock
	.clk			(clk_ref),		//100MHz clock
	.rst_n			(sys_rst_n),	//global reset
	
	//mcu spi interface
	.spi_cs			(spi_cs),		//Chip select enable, default:L
	.spi_sck		(spi_sck),		//Data transfer clock
	.spi_mosi		(spi_mosi),		//Master output and slave input
//	.spi_miso		(spi_miso),		//Master input and slave output

	//user interface	
	.rxd_flag		(rxd_flag),
	.rxd_data		(rxd_data)
);


//---------------------------------------
//Transfer SPI Data to mcu.
wire	txd_flag;
spi_transfer u_spi_transfer
(
	//global clock
	.clk			(clk_ref),		//100MHz clock
	.rst_n			(sys_rst_n),	//global reset
	
	//mcu spi interface
	.spi_cs			(spi_cs),		//Chip select enable, default:L
	.spi_sck		(spi_sck),		//Data transfer clock
//	.spi_mosi		(spi_mosi),		//Master output and slave input
	.spi_miso		(spi_miso),		//Master input and slave output

	//user interface		
	.txd_en			(rxd_flag),
	.txd_data		(rxd_data),
	.txd_flag		()		
);


//---------------------------------
//led data input with enable signal.
wire	[7:0]	led_data;
led_input_display
#(
	.LED_WIDTH	(8)
)
u_led_input_display
(
	//global
	.clk				(clk_ref),		//100MHz clock
	.rst_n				(sys_rst_n),    //global reset
	
	//user interface
	.led_en				(rxd_flag),
	.led_value			(rxd_data),
	
	//led interface
	.led_data			(led_data)
);

//---------------------------
//The driver of 74HC595
led_74595_driver	u_led_74595_driver
(
	//global clock
	.clk				(clk_ref),
	.rst_n				(sys_rst_n),

	//74hc595 interface
	.led595_dout		(led595_dout),	//74hc595 serial data input	
	.led595_clk			(led595_clk),	//74hc595 shift clock (rising edge)
	.led595_latch		(led595_latch),	//74hc595 latch clock (rising edge)

	//user interface
	.led_data			(led_data)		//led data input	
);


endmodule

